The initial PSW is stored in data memory 0 prior to starting the processor and dumped to data memory 5 by the SSP Linker.
______________________________________________________ | | | | | | | | | | | | | | | | | |I|E|T| S |B|E|A|MS|R|W|EX|N|S|O|CC| PC | |N|X|O| S |R|G|S| |D|A| |P|M|M| | (program counter) | |T|C|U| |E| |A| | |I| |A|S|S| | | |R|P|T| |Q| |K| | |T| | |K|K| | | | | | | | | | | | | | | | | | | | ______________________________________________________bits 0:11 - PC = program counter 12:13 - CC = IBM encoded condition code
14 - OMSK = IBM overflow mask 15 - SMSK = IBM system mask 16 - NPA = Next PROM address (multiple cycle)
17:18 - EX = 0 if divide by zero 1 if overflow 2 if unsupported opcode
19 - WAIT = WT being asserted at time of error 20 - RD = 0 if write in progress at time of error 1 if read in progress at time of error
21:22 - MS = Mode select bits 0,1 at time of error
23 - ASAK = ASAK lock present at time of error 24 - EG = Address cycle in progress at time of error 25 - BREQ = Arbitration cycle in progress at time of error
26:28 - SS = Slave status at time of I/O error
29 - TOUT = Timeout during FASTBUS operation 30 - EXCP = Exception (see EX bits description) 31 - INTR = External interrupt (attached as FASTBUS slave)
CSR (0000,0000) = Mfg. ID. and control/status bits
__________________________________________________________ |Bit#|Power-on| Meaning on READ | Meaning on WRITE | | | value | when bit set | when bit set | |----|--------|---------------------|----------------------| | 0 | 0 | | | | 1 | 0 |Crate selected for RB| Select crate for RB | | 2 | 0 | RUN enabled | Enable RUN state | | 3 | 0 | RB asserted Assert RB | |----|--------|---------------------|----------------------| | 4 | 0 |Crate selected for SR| Select crate for SR | | 5 | 0 | SR asserted | Assert SR | | 6 | 0 | Single step enabled | Enable single step | | 7 | 0 | GKUP (maintain GK) | Enable GKUP | |----|--------|---------------------|----------------------| | 8 | 0 | Crate seg. selected | Select crate segment | | 9 | 0 | SR enabled (cable) | Enable SR (cable) | | 10 | 0 | Timeout inhibited | Enable TO inhibit | | 11 | 0 | | Start processor | |----|--------|---------------------|----------------------| | 12 | ? | CLASS device | >Set 'N' (CLASS bits)| | 13 | ? | defined on 4 bits | > | | 14 | ? | used in broadcast | > if enabled | | 15 | ? | case #1 | > | |----|--------|---------------------|----------------------| | 16 | 0 | Mfg. ID. (106 hex) | Enable SET CLASS bits| | 17 | 1 | Mfg. ID. | Select cable for RB | | 18 | 1 | Mfg. ID. | Disable RUN state | | 19 | 0 | Mfg. ID. | Lower RB | |----|--------|---------------------|----------------------| | 20 | 0 | Mfg. ID. | Disable SR (cable) | | 21 | 0 | Mfg. ID. | Lower SR | | 22 | 0 | Mfg. ID. | Disable single step | | 23 | 0 | Mfg. ID. | Disable GKUP | |----|--------|---------------------|----------------------| | 24 | 1 | Mfg. ID. | Select cable segment | | 25 | 0 | Mfg. ID. | Disable SR (cable) | | 26 | 0 | Mfg. ID. | Disable TO inhibit | | 27 | 0 | Mfg. ID. | | |----|--------|---------------------|----------------------| | 28 | 0 | Mfg. ID. | | | 29 | 0 | Mfg. ID. | | | 30 | 0 | Mfg. ID. | | | 31 | 0 | Mfg. ID. | | __________________________________________________________CSR (0000,0008) = Arbitration level
The following locations in PM space are reserved by the hardware:
CSR (4000,0000) through CSR (4000,0FFF) = 4K words Reserved locations
__________________________________________________________ | FASTBUS | CPU program | Contents | | CSR Space | memory address | | | address | | | |-----------|----------------|-----------------------------| | 4000-0000 | 0 | Exception handler trap addr | | 4000-0001 | 1 | Reserved | | . | . | . | | . | . | . | | . | . | . | | 4000-007F | 7F | Reserved | __________________________________________________________
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