EN_LOG_ADDR
This enables logical addressing, by writing a '1' to bit 1 in CSR 0
of the Branch driver.
DEV_ALLOC
This allocates the device by writing a '1' to bit 3 in CSR 0
of the Branch driver.
SR_EN
This enables SR (service request) assertion, by writing a '1' to
bit 4 in CSR 0 of the Branch driver.
SR_ASS
This asserts SR (service request) by writing a '1' to bit 5 in CSR 0
of the Branch driver.
SET_SS7_EN
Sets the mode (SS=7 if no X) by writing a '1' to bit 6 in CSR 0 of Branch
driver.
SET_Q_BIT0
Set Q-mode Bit 0 by writing a '1' to bit 7 in CSR 0 of Branch driver.
SET_Q_BIT1
Set Q-mode Bit 1 by writing a '1' to bit 8 in CSR 0 of Branch driver.
SET_BLK_BIT0
Set CAMAC block mode Bit 0 by writing a '1' to bit 9 in CSR 0 of
Branch driver.
SET_BLK_BIT1
Set CAMAC block mode Bit 1 by writing a '1' to bit 10 in CSR 0 of
Branch driver.
WAIT_EN
Set WAIT mode by writing a '1' to bit 11 in CSR 0 of Branch driver.
CLR_TIMOUT
Clear timeout error by writing a '1' to bit 16 in CSR 0 of Branch
driver.
DI_LOG_ADDR
Disable logical addressing by writing a '1' to bit 17 in CSR 0 of
Branch driver.
DEV_DEALL
Deallocate device by writing a '1' to bit 19 in CSR 0 of Branch driver.
SR_DI
Disable SR (service request) assertion by writing a '1' to bit 20 in
CSR 0 of Branch driver.
SR_RESET
Reset SR (service request) by writing a '1' to bit 21 in CSR 0 of
Branch driver.
CLR_SS7_EN
Clear mode ( SS=7 if no X ) by writing a '1' to bit 22 in CSR 0 of
Branch driver.
CLR_Q_BIT0
Clear Q-mode Bit 0 by writing a '1' to bit 23 in CSR 0 of Branch
driver.
CLR_Q_BIT1
Clear Q-mode Bit 1 by writing a '1' to bit 24 in CSR 0 of Branch
driver.
CLR_BLK_BIT0
Clear CAMAC block-mode Bit 0 by writing a '1' to bit 25 in CSR 0 of
Branch driver.
CLR_BLK_BIT1
Clear CAMAC block-mode Bit 1 by writing a '1' to bit 26 in CSR 0 of
Branch driver.
WAIT_DI
Clear WAIT mode by writing a '1' to bit 27 in CSR 0 of Branch driver.
RESET
RESET the Branch driver by writing a '1' to bit 30 in CSR 0 of Branch
driver. This command clears logical addressing.
CAMAC_Z
Initialize CAMAC Z operation by writing a '1' to bit 31 in CSR 0 of
Branch driver.
READ_CSR0
This command reads and interprets CSR 0 of the Branch driver. The most
significant 16 bits contain the manufacturer's ID. After setting or
clearing the available functions in CSR 0 (see HELP BRANCH MENU) the
present status of these functions is output by this command.
READ_CSR1
This command reads CSR 1 of the Branch driver, which results in a
CAMAC graded LAM operation (Read only).
READ_CSR3
This command reads CSR 3 of the Branch driver, which is the logical
address register (Read/Write). The logical address is written to this
register the first time the CFIMENU commands BRDRV or CAMAC is given.
READ_CSR7
This command reads CSR 7 of the Branch driver, which is the broadcast
class N register (Read/Write only). See STR320 manual for details.
To write to CSR7, exit from BRDRV to CFIMENU, and use the command FWC.
TST_ALIAS
This command is for test purposes only.
EXIT
Returns control to CFIMENU
MENU
Outputs the menu of the BRDRV subroutine.
COMMAND_FILE
An example of the format to use the command BRDRV in a command file is
shown:
! BRDRV.CCM ! CFIMENU commands and BRDRV commands can have inline comments. BRDRV ! branch driver in slot D - use default logical address DCAMAC_Z ! perform CAMAC Z READ_Csr0 ! read CSR 0 SR_EN ! enable SR SET_Q_BIT1 ! set Q mode bit 1 SET_BLK_bit0 ! set block mode bit 0 read_csr0 ! read CSR 0 reset ! reset branch driver ex ! exit from BRDRV back to CFIMENU
See HELP @ for information on using command files.