The set of general registers starting with the register specified by R1 and ending with the register specified by R3 is loaded from the locations designated by the second-operand address.
The storage area from which the contents of the general registers are obtained starts at the location designated by the second-operand address and continues through as many locations as needed. The general registers are loaded in the ascending order of their addresses, starting with the register specified by R1 and continuing up to and including the register specified by R3, with register 0 following register 15.
The code remains unchanged.
Access (fetch, operand 2)
All combinations of register addresses specified by R1 and R3 are valid. When the register addresses are equal, only one word is transmitted. When the address specified by R3 is less than the address specified by R1, the register addresses wrap around from 15 to 0.