The address specified by the X2, B2, and D2 fields is inserted in bit positions 23-0 of the general register specified by the R1 field. Bits 24-31 of the register are set to zeros. The address computation follows the rules for address arithmetic.
No storage references for operands take place, and the address is not inspected for access exception
Resulting Condition Code:
The code remains unchanged.
The same general register may be specified by the RI, X2, and B2 instruction field, except that general register 0 can be specified only by the R1 field. ln this manner it is possible to increment the low-order 24 bits of a general register, other than 0, by the contents of the D2 field of the instruction. The register to be incremented should be specified by R1 and by either X2 (with B2 set to zero) or B2 (with X2 set to zero).