The double-length integer part of the first operand is shifted right the number of places specified by the second-operand address. Bits 16-19 of the instruction are ignored.
The R1 field of the instruction specifies an even-odd pair of registers and must designate an even numbered register. When R1 is odd, a specification exception is recognized.
The second-operand address is not used to address data; its low-order six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored.
The first operand is treated as a number with 63 integer bits and a sign in the sign position of the even register. The sign remains unchanged. The high-order position of the odd register contains an integer bit, and the contents of the odd register participate in the shift in the same manner as the other integer bits. The low-order bits are shifted out without inspection and are lost. Bits equal to the sign are supplied to the vacated positions of the registers.
Resulting Condition Code:
0 ~ Result is zero
1 ~ Result is less than zero
2 ~ Result is greater than zero
3 ~ -
Program Exceptions:
Specification