The double-length first operand is shifted left the number of bits specified by the second-operand address. Bits 16-19 of the instruction are ignored.
The R1 field of the instruction specifies an even-odd pair of registers and must designate an even-numbered register. When R1 is odd, a specification exception is recognized.
The second-operand address is not used to address data; its low-order six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored.
All 64 bits of the first operand participate in the shift. High-order bits are shifted out of the even-numbered register without inspection and are lost. zeroes are supplied to the vacated positions of the registers.
Resulting Condition Code:
The code remains unchanged.
Program Exceptions:
Specification