The double-length integer part of the first operand is shifted left the number of bits specified by the second-operand address. Bits 16-19 of the instruction are ignored.
The R1 field of the instruction specifies an even-odd pair of registers and must designate an even numbered register. When R1 is odd, a specification exception is recognized.
The second-operand address is not used to address data; its low-order six bits indicate the number of bit positions to be shifted. The remainder of the address is ignored.
The first operand is treated as a number with 63 integer bits and a sign in the sign position of the even register. The sign remains unchanged. The low-order position of the odd register contains an integer bit, and the contents of the odd register participate in the shift in the same manner as the other integer bits. Zeros are supplied to the vacated positions of the registers.
If a bit unlike the sign bit is shifted out of bit position 1 of the even register, an overflow occurs. The overflow causes a program interruption when the fixed-point overflow mask bit is one.
Resulting Condition Code:
0 ~ Result is zero
I ~ Result is less than zero
2 ~ Result is greater than zero
3 ~ Overflow
The eight shift instructions provide the following three pairs of alternatives: left or right, single or double, and algebraic or logical. The algebraic shifts differ from the logical shifts in that, in the algebraic shifts, overflow is recognized, the condition code is set, and the high-order bit participates as a sign.
The maximum shift amount which can be specified is 63. For algebraic shifts this is sufficient to shift out the entire integer field. Since 64 bits participate in the double-logical shifts, the entire register contents cannot be shifted out.
A zero shift amount in the two algebraic double-shift operations provides a double-length sign and magnitude test. The base register participating in the generation of the second-operand address permits indirect specification of the shift amount. A zero in the B2 field indicates the absence of indirect shift specification.
See Extended Mnemonic Instructions on page