An increment is added to the first operand, and the sum is compared algebraically with a comparand. Subsequently, the sum is placed in the first-operand location, regardless of whether the branch is taken. The second-operand address is used as the branch address.
When the sum is low or equal, the instruction address in the current PSW is replaced by the branch address. When the sum is high, normal instruction sequencing proceeds with the updated instruction address.
The first operand and the increment are in the registers specified by R1 and R3. The comparand register address is odd and is either one larger than R3 or equal to Rx. The branch address is computed before the addition and comparison.
This instruction is similar to BRANCH ON INDEX HIGH, except that the branch is successful when the sum is low or equal compared to the comparand.
Resulting Condition Code:
The code remains unchanged.