The contents of the general register specified by R1 are algebraically reduced by one. When the result is zero, normal instruction sequencing proceeds with the updated instruction address. When the result is not zero, the instruction address in the current PSW is replaced by the branch address.

In the RX format, the second-operand address is used as the branch address. In the RR format, the contents of bit positions 23-0 of the general register specified by R2 are used as the branch address. However, when the R2 field contains zeros, the operation is performed without branching.

The branch address is computed before the counting operation. Counting does not change the condition code. The overflow occurring on transition from the maximum negative number to the maximum positive number is ignored. Otherwise, the subtraction proceeds as in fixed-point arithmetic, and all 32 bits of the general register participate in the operation.

Resulting Condition Code:

The code remains unchanged.

Program Exceptions

None

Programming Notes

An initial count of one results in zero, and no branching takes place;
an
initial count of zero results in minus one and causes branching to be
executed;
an initial count of minus one results in minus 2 and causes branching
to be
executed; and so on. In a loop, branching takes place each time the
instruction
is executed until the result is again zero. Note that, because of the
number
range, an initial count of minus 231 results in the positive value of
211.

Counting is performed without branching when the R2 field in the RR format contains zero.

*Branch on Index High*

An increment is added to the first operand, and the sum is compared algebraically with a comparand. Subsequently, the sum is placed in the first-operand location, regardless of whether the branch is taken. The second-operand address is used as the branch address. When the sum is high, the instruction address in the current PSW is replaced by the branch address. When the sum is low or equal, instruction sequencing proceeds with the updated instruction address.

The first operand and the increment are in the registers specified by R1 and R3. The comparand register address is odd and is either one larger than R3 or equal to R3- The branch address is computed before the addition and comparison.

Overflow caused by the addition is ignored and does not affect the comparison. Otherwise, the addition and comparison proceed as in fixed-point arithmetic. All 32 bits of the general registers participate in the operations, and negative quantities are expressed in two's-complement notation. When the first operand and comparand locations coincide , the original register contents are used as the comparand.

Resulting Condition Code:

The code remains unchanged.

Program Exceptions:

None

Programming Note

The name ``branch on index high'' indicates that one
of the major purposes of this instruction is the incrementing and
testing of an
index value. The increment may be algebraic and of any magnitude.