The updated instruction address in the current PSW is replaced by the branch address if the state of the condition code is as specified by M1; otherwise, normal instruction sequencing proceeds with the updated instruction address.
In the RX format the second-operand address is used as the branch address. In the RR format the contents of bit positions 23-0 of the general register specified by R2 are used as the branch address. However , when the R2 field contains zeros, the operation is performed without branching.
The M1 field is used as a four-bit mask. The four bits of the mask correspond, left to right, with the four condition codes (0, 1, 2, and 3), as follows:
Bit Mask Condition Code 8 8 0 9 4 1 10 2 2 11 1 3
The branch is successful whenever the condition code has a corresponding mask bit of one.
When the M1 and R2 fields of BCR are 15 and 0, respectively, a serialization function is performed. CPU operation is delayed until all previous storage accesses by this CPU to main storage have been completed, as observed by channels and other CPUs. No subsequent instructions or their operands are accessed by this CPU until the execution of this instruction is completed.
Resulting Condition Code:
The code remains unchanged.
Program Exceptions:
None
Programming Notes
When a branch is to be made on more than one condition code, the
pertinent
condition codes are specified in the mask as the stun of their mask
position
values. A mask of 12, for example, specifies that a
branch is to be made on condition codes 0 and 1.
When all four mask bits are zero or when the R2 field in the RR format
contains zero, the branch instruction is equivalent to a no-operation.
When
all four mask bits are ones, that is, the mask value is 15, the branch
is
unconditional unless the R field in the RX format is zero.
Note that the relation between the RR and RX formats in branch-address specification is not the same as in operand-address specification. For branch instructions in the RX format, the branch address is the address specified by X2, B2, and D2; in the RR format, the branch address is in the low-order 24 bits of the register specified by R2. For operands, the address specified by X2, B2, and D2 is the operand address, but the register specified by R2 contains the operand itself.