Information from the current PSW, including the updated instruction address, is loaded as link information in the general register designated by R1. Subsequently, the instruction address is replaced by the branch address.
In the RX format, the second-operand address is used as the branch address. In the RR format, the contents of bit positions 23-0 of the general register designated by R2 are used as the branch address. In the IBM 370, when the R2 field contains zeros, the operation is performed without branching. In the SSP, the assembler translates such an instruction to a BAL0 or BALR0 opcode.
The branch address is computed before the link information is loaded. The link information, in both the BC and EC modes, consists of the condition code , the program mask bits, and the updated instruction address, arranged in the following format:
Resulting Condition Code:
The code remains unchanged.
Program Exceptions:
None