FASTBUS I/O:

1. All FASTBUS cycles having a Primary Address will always perform a BUS Arbitration.

2. All FASTBUS cycles having a Primary Address will drop and re-establish the AS/AK lock.

3. Any non-I/O instruction will break the AS/AK lock, with the exception of the `F' series instructions; see page .

4. All FASTBUS cycles returning an SS code other than 0 will cause an error with the exception of block transfers that normally terminate with an SS=2.

5. A Data-Memory wrap-around during any FASTBUS block transfer will generate an error.

6. The R1 field is ignored for all FASTBUS I/O except during Primary Address cycles. During a Primary Address cycle, the two LSB of R1 are used to select the MS code as shown in Table 6.

Table 6: Address Time MS Codes

MS    Address Mode                               
00    Specific device  - Data space              
01    Specific device  - CSR  space              
10    Broadcast        - Data space              
11    Broadcast        - CSR  space