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The normal sequential execution of instructions may be changed by the use of the branching instructions in order to perform subroutine linkage , decision making, and loop control.

Subroutine linkage is provided by the BRANCH AND LINK instructions, which permit not only the introduction of a new instruction address but also the preservation of the return address and associated information.

Facilities for decision making are provided by the BRANCH ON CONDITION instruction. This instruction inspects a two-bit condition code that reflects the result of a majority of the arithmetic, logical, and I/0 operations. Each of these operations can set the code in any one of four states, and the instruction BRANCH ON CONDITION can specify any selection of these four states as the criterion for branching. For example, the condition code reflects such conditions as nonzero, first operand high, equal, overflow, and zero. Once set, the condition code remains unchanged until modified by an instruction that causes a different condition code to be set.

The two bits of the condition code provide for four possible condition code settings: 0, 1 , 2, and 3. The specific meaning of any setting depends on the operation that sets the condition code.

Loop control can be performed by the use of BRANCH ON CONDITION to test the outcome of address arithmetic and counting operations. For some particularly frequent combinations of arithmetic and tests, the instructions BRANCH ON count and BRANCH ON INDEX are provided. These branches, being specialized, provide increased performance for these tasks.

The interruption system permits the CPU to change state as a result of conditions external to the system, in input/output (I/0) units, or in the CPU itself. Four classes of interruption conditions are possible : machine check (divide by zero), program, external (FASTBUS access), and FASTBUS error.

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