Bit 31 of the PSW indicates that the I/O-Error Handler was entered because of an I/O Interrupt. It is the responsibility of the I/O-Error Handler to put the SSP to `sleep' by writing to CSR0 and resetting the RUN bit.
If the System Mask is ON and a Master attempts to attach to the SSP, the SSP will return AK and WT during the Primary Address cycle. WT will be released only after the I/O-Error Handler has reset the RUN bit in CSR0.
If the System Mask is OFF and a Master attempts to attach to the SSP, the SSP will return AK during the Primary Address cycle. The SSP will return an SS=1, BUSY, for any subsequent address or data cycles.
To continue executing the program from the point it was interrupted, DM 0 must be loaded with the correct PSW. This PSW is either the same PSW that was loaded into DM 0 when the interrupt occurred, or one less than it. The NPA Bit in the PSW indicates whether to subtract 1 or not. If the NPA Bit is 1, subtract 1, otherwise subtract 0. After the correct PSW is loaded into DM 0, set the RUN Bit and the Start Bit in CSR#0 to continue execution.
To start the SSP running in a different location than where the interrupt occurred, load the desired PSW into DM 0. Then set the RUN and Start Bit in CSR#0 to start the SSP.