Table 1: Format of CSR#0
Bit Hex Read Write
31 80000000 EPM
30 40000000 Bits 16-31 Reset (disable Class N)
29 20000000 Manufacturer's
28 10000000 I.D. EPM
27 08000000 0106 (no EPM) Enable Class
26 04000000 Enable Time-outs
25 02000000 0107 (with EPM) Disable CI SR
24 01000000 Enable CI Mastership
23 00800000 Disable Hold GK
22 00400000 Disable CSR#0<6>
21 00200000 Reset SR
20 00100000 Disable CR SR
19 00080000 Reset CSR#0<3>
18 00040000 Reset Soft Halt, HALT
17 00020000 Enable CI CSR#0<3>
16 00010000 EPM enabled Enable writing of Class
15
14 0000X000 Bits 12-15 Bits 12-15
13 Class for case 2 Set Class for case 2
12 Broadcasts Broadcasts
11 00000800 Class N enabled Trigger
10 00000400 Time-outs Disabled Disable Time-outs
09 00000200 CI SR Enabled Enable CI SR
08 00000100 CR Mastership Enabled Enable CR Mastership
07 00000080 Hold GK Enabled Enable Hold GK
06 00000040 Single cycle mode Set CSR#0<6>
05 00000020 SR set (DONE) Set SR
04 00000010 CR SR Enabled Enable CR SR
03 00000008 Cable SR is set Set CSR#0<3>
02 00000004 RUN Bit Set Set Soft Halt Bit
01 00000002 Crate SR is set Enable CR CSR#0<3>
00 00000001 Power fault Set Soft Halt
CR - Crate segment, CI - Cable segment