CPU:

• 32 Bit
• Emulates IBM integer machine language instructions. All instructions are 32 bits long.
• Separated Data and Program memory.
• Executes single or combined FASTBUS I/O operations.
• Basic cycle time of 100 ns. Narrowed to 80 during multiply, divide, and shifts.
• Users I/O and Error handler starts at location 0 in Program memory. Updated PSW in location 0 in data memory. Memory Address register contents in location 4 in Data memory.
• I/O INTERRUPT from either the Crate or Cable segment at the end of an instruction or group of I/O instructions. System Mask must be on.