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Contents

• Contents
• List of Tables
• List of Figures
• 1 INTRODUCTION
• 2 DESCRIPTION OF PCL SUBSYSTEMS
  • 2.1 GENERAL
  • 2.2 PRIMARY ADDRESS CONTROL
  • 2.3 DATA CYCLE CONTROL
  • 2.4 TIMING CONTROL
  • 2.5 USER SIDE ARBITRATION
• 3 PCL SIGNAL SUMMARY
  • 4.1 SEGMENT SIGNALS
  • 3.2 ADI SIGNALS
  • 3.3 TRANSCEIVER CONTROL SIGNALS
  • 4.3 TIMING SIGNALS
  • 3.5 USER SIGNALS
    • 3.5.1 Configuration
    • 3.5.2 Status
    • 3.5.3 Control
    • 3.5.4 Arbitration
    • 3.5.5 CSR#0
    • 3.5.6 Master
• 4 PCL SIGNAL DETAILS
  • 4.1 SEGMENT SIGNALS
  • 4.2 PCL - ADI INTERCONNECT SIGNALS
  • 4.3 TIMING SIGNALS
    • 4.3.1 Details of PCL timing
  • 4.4 USER CONTROL SIGNALS
  • 4.5 USER STATUS SIGNALS
  • 4.6 CSR#0 INTERFACE SIGNALS
  • 4.7 CONFIGURATION INPUTS
  • 4.8 USER ARBITRATION SIGNALS
  • 4.9 MASTER INTERFACE SIGNALS
• 5 PCL Mechanical Data
• 6 PCL ELECTRICAL CHARACTERISTICS
  • 6.1 Propagation Delays
  • 6.2 Operating Characteristics
  • 6.3 DC Characteristics
  • 6.4 AC Characteristics
• 7 ADI OPERATION
  • 7.1 Major Elements of the ADI
  • 7.2 ADI Description
    • 7.2.1 Data Bus and Multiplexer
    • 7.2.2 Data Latch
    • 7.2.3 Fastbus Data Buffer
    • 7.2.4 User Data Buffer
    • 7.2.5 Geographic Address Check
    • 7.2.6 Internal Address Width Decode
    • 7.2.7 Logical Address Register (CSR#3)
    • 7.2.8 Logical Address Check
    • 7.2.9 Class N Register (CSR#07)
    • 7.2.10 Class N Decoder and Check
    • 7.2.11 Next Transfer Address Register
    • 7.2.12 User Address Driver
    • 7.2.13 Parity Check
    • 7.2.14 Address Decoder
  • 7.3 ADI Signal Description
    • 7.3.1 Strobes
    • 7.3.2 Tristate Controls
    • 7.3.3 Inversion Control
• 8 ADI Mechanical Data
• 9 ADI ELECTRICAL CHARACTERISTICS
• 10 DESIGN TOOLS
• 11 Application notes
  • 11.1 Application Note #1 - Using OBPS
  • 11.2 Application Note #2 - Implementing Read-Only Locations
  • 11.3 Application Note #3 - Reset and Clear Signals
  • 11.4 Application Note #4 - Use of the Protective Buffer
  • 11.5 Application Note #5 - Advanced and CERN Modes
  • 11.6 Application Note #6 - User Side Arbitration
  • 11.7 Application Note #7 - Defeating Parity Logic
  • 11.8 Application Note #8 - Multiblock operation
  • 11.9 Application Note #9 - Use of IBSY
  • 11.10 Application Note #10 - Board Layout
  • 11.11 Application Note #11 - Broadcast Operations
    • 11.11.1 Disconnect on Unimplemented Secondary Address
    • 11.11.2 SS codes
  • 11.12 Application Note #12 - Implementing a Master
  • 11.13 Application Note #13 - Use of IFAT for Broadcast Case 8
  • 11.14 Application Note #14 - Example of CSR#0 Implementation
  • 11.15 Application Note #15 - Implementing an Address Decoder
  • 11.16 Application Note #16 - Simple FASTBUS Slave Implementation
• A PRELIMINARY SPECIFICATION FOR FASTBUS MULTIBLOCK MODE.
  • A.1 General Description
  • A.2 Multiblock Configuration.
  • A.3 Multiblock Capable Slaves.
  • A.4 Multiblock Control Signals.
  • A.5 Multiblock Operation.
  • A.6 Re-Access In Multiblock Mode.
• Index
• About this document ...