7.3.1 Strobes

• ICNR
  Load Class N Register: Input.
  When high, data from the data bus is freely passed into CSR#07. Upon going low, data which meets the set-up time of CSR#07 is held in the latch.

• IEL
  Enable Latch: Input.
  When high the data latch is in the transparent mode. Upon going low, data which meets the set-up time of the data latch is held in the latch. The latch output, and therefore the BB or BD outputs will not change until IEL goes high again.

• ILAR
  Load Logical Address Register: Input.
  When high, data from the data bus is freely passed into CSR#03. Upon going low, data which meets the set-up time of CSR#03 is held in the latch.

• INLN
  Load Next Transfer Address Register: Input.
  The falling (negative going) edge of this signal loads data which meets the set-up time from the NTA multiplexer, into the NTA register.