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7.2.13 Parity Check

A parity checking circuit is connected to the data bus. At times other than when the NTA is being incremented, parity information is cascaded between the chips and passed to the external control logic on the BGPC and OCP pins.



Next: 7.2.14 Address Decoder Up: 7.2 ADI Description Previous: 7.2.12 User Address Driver


A.Daviel,TRIUMF