This is a sixteen-bit wide register which is negative edge loaded by INLN.
It takes its data from a three input multiplexer controlled by IAMA and IAMB.
One input to the multiplexer is the full data bus for secondary address
loading. The second input is the data bus, via a mask controlled by the
internal address width setting, for internal address loading. The third
input is the output of the NTA register via a fast adder, for incrementing
the NTA during block transfers. The adder has carry input and output. These
are multiplexed with the geographic address check output and the parity
signals on the BGPC and OCP
pins. The carry output is
passed to the OCP pin only during an increment NTA operation. When INLC is
low (in the case of the lower ADI chip) the carry input is held high. When
INLC is high, and only during an increment NTA operation, carry in is
obtained through the BGPC pin, which should be externally connected to the
OCP pin of the lower chip.