4.6 CSR#0 INTERFACE SIGNALS

• IC01 - CSR#.
  Should be connected to CSR#0 (output of J-K flipflop). This is the Logical Addressing enable bit. The user must provide the parts of CSR#0 which are needed. If Logical Addressing is to be used, bit 1 must be present, and its output connected to this input. The PCL checks that this input is high before attaching upon recognition of a Logical Address. If Logical Addressing is not used IC01 and ILAC should be tied low. See example in Section 11.14.

• IC05 - CSR#0.
  See ISR.
• ISR - Service Request, IC05 CSR#0.
  If SR is to be used then Service Request logic, including the SR segment driver and CSR#0 bit 5, must be provided. The output of CSR#0 (SR Flag) is connected to IC05. The signal driving the SR segment driver (not the state of the SR segment line) is connected to ISR. The PCL uses these signals to generate the T pin responses to Broadcast Cases 5 and 6. If SR will not be asserted then tie these two lines low.

• ONCL - Clear.
  This signal is generated from Power-on-Clear or (Reset Bus and not Bus Halted) or Write CSR#. It may be used to clear CSR# and CSR#. See the FASTBUS Specification, table 8.18, page 8-15. See Section 11.3 for an application note.

• ONPE - Parity Error.
  This goes low if a parity error is detected. It may be used to set CSR#, the Parity Error Bit.

• ONRS - Reset.
  This signal is generated from Power-on-Clear or Write CSR#. It may be used to clear most CSR bits except CSR# and CSR#. See the FASTBUS Specification, table 8.18, Page 8-15. See Section 11.3 for an application note.

• ONRZ - Read CSR#0, ONWZ Write CSR#0.
  These active low outputs are used to read and write CSR#0, which should consist of J-K flipflops with a positive edge clock and tri-state buffers (for readback) with low output enables. See Section 11.14 for an application note.