4.4 USER CONTROL SIGNALS

• IAC(2:0) - Next Transfer Address Code.
  The user is required to provide an internal NTA decoder which examines the output of the NTA register (ADI OA(31:00) and/or OACA, OACB), OCND and optionally ORD and OMS(2:0). It indicates to the PCL if the address is valid, where it is located and whether it is RAM or FIFO memory. This information is encoded on IAC(2:0); see Table 3.

  

  

  A simple Slave which uses only RAM type user locations, CSRs#0 and 3 may tie IAC2 low and provide just two signals from the NTA decoder to IAC(1:0). A more complex Slave with FIFO locations, or CSR#4 or 7 must drive all three inputs. Addresses which are not implemented must produce the `Not Used' code (2). This will cause the PCL to produce the appropriate SS response. The user's NTA decoder also controls the user's registers, along with the ORD and OUST signals. The effect of indicating that a register is a FIFO prevents incrementing of the NTA during Block and Pipeline transfers. To indicate the end of data or locations in a FIFO register the user must change IAC(2:0) to `End of FIFO'. If a `Not Used' address is arrived at by means of a Block or Pipelined Transfer, then subsequent Block or Pipelined transfers will produce SS=2. If a Single Transfer is attempted to or from a `Not Used' address, an SS=6 is produced. If a Block or Pipelined operation with a `Not Used' address is attempted after a Single Transfer or Secondary Address operation, then an SS=6 is generated. The CSR#4 code uses the `class' register (CSR#7) in a `Device User Address Register' mode. If this application is preferred in place of Class N Broadcast addressing, the CSR#7 code should not be produced by the NTA decoder, and the INCN line tied high.

  See Section 11.15 for an example of an NTA decoder.

• IACT - Accept.
  IACT forces acceptance of any data received with parity error. If not used it should be tied low. The PCL has a standard response of SS=6 (data rejected) to a write parity error during Data Cycles. The Master is expected to retry the operation to correct the error. If the Master ignores SS=6 and does not retry during a Block Transfer or Pipelined Transfer, then all data following the error will be mis-located. The user may opt to respond with SS=7 (accept the bad data), and thus maintain Block or Pipelined data synchronism, by setting IACT high for any particular address and MS combination. This signal is best generated by the user's NTA decoder, since it is probably not desireable for all CSR registers.

• IBSY - Busy.
  When high causes an SS=1 response to all Data Cycles; no user signals are generated. If the Slave contains locations which cannot respond to an operation within the response time of the segment, the user may assert IBSY to the PCL. SS=1 will then be sent to the Master, and no further action will be taken by the interface. For more detail, see section 11.9. If IBSY is not used it should be tied low.

• IDA - Device Available.
  This is the ``device available'' flag which is used in Broadcast Case 3a to control the T pin response. If IDA is high during a Broadcast Case 3a read cycle the T-Pin is asserted; see the FASTBUS Specification Section 4.3.2. If IDA is not used it should be tied low.

• IDP - Data Present.
  This is the ``data present'' flag which is used in Broadcast Case 3 to control the T pin response. If IDA is high during a Broadcast Case 3 read cycle the T-Pin is asserted; see the FASTBUS Specification Section 4.3.2. If IDA is not used it should be tied low.

• IFAT - Force Attach.
  A high level on this input at Primary Address time (AS(u)) will cause the Slave to become attached in the Broadcast mode (no DK generated) to the current Master. It will stay attached until AS(d). This may be used to implement Broadcast Case 8 (manufacturer's mode). The user must examine IAK, MS(2:1) and the AD lines. When the appropriate pattern is detected IFAT should be driven high; see Section 11.13 for an application note.

  A high level on this input when the Slave is already attached will cause the PCL to inhibit the DK response and user data cycles (while still asserting AK). A high level on this input when the Slave is not attached and AK=1 will cause the PCL to issue the DK response and generate user data cycles (as if it were attached). This feature is used in Multiblock mode; see Section 11.8 for an application note.

• IPOC - Power on Clear.
  When low this will clear the Class N register in the ADIs, assert the ONRS and ONCL output signals, and ensure that the PCL is in the unattached condition. It should be driven by the power-on-clear circuit of the Slave. A low condition for 200ns or more will perform the reset. Hold high at all other times. See section 11.3 for applications.

• ISSD - Slave Status Disable, IUS(2:0) User SS Code.
  SS code generation is automatic for most cases. When something other than the normal response is required, the user may place the required pattern on IUS(2:0). To prevent this pattern being OR-ed with the normal response, driving ISSD high will suppress the internally generated SS code. Tie these lines low if not used. The SS codes are generated according to a priority scheme (6 being highest priority), as shown in Table 4 on page .