All segment signals are connected to the FASTBUS segment via TTL/ECL translators except for the following:
IASD is driven by the AS signal via a delay of typically 80ns which allows for propagation delays through the address detection circuits. An RC integrator is satisfactory (1.0k and 100pF).
IAS is driven by the AS signal via a small integrator (typical 10ns) as detailed in the FASTBUS specification Appendix A.
IDS is driven by the DS signal via a small integrator (typical 10ns) which allows for propagation delay through the MS decoders within the PCL.
IRBI is driven by RB via an integrator (500ns for a Crate Segment).
ODK drives DK via a small delay which allows the removal of data from the AD lines on a cleanup cycle.
The above inputs are Schmitt Trigger type, therefore a series resistor and capacitor to ground are adequate. See the FASTBUS specification for the significance of all other signals.
See Table 1 on page for suggested values for the integrator components.
OWT is driven by the user side arbitration logic in the PCL. If this feature is used, OWT should be OR-ed with any other wait source in the Module, and used to drive Segment WT (See Section 11.6 for an application note).