The PCL provides all dynamic control signals for the ADI chips. Full parity checking is performed. This may be easily defeated if desired; see Section 11.7. The PCL responds automatically to the WT signal. The user may assert the WT signal which will control both his PCL and other FASTBUS devices. A ``Master'' input (from the user or Master arbitration circuit) controls the data flow through the ADIs to allow a Master to use the data latch and parity generator in the ADIs.