The bus arbitration is designed so that if IBSY=1 the PCL may complete
FASTBUS cycles by giving SS=1 without using the internal busses OA, BD. If
IBSY=0 the PCL will arbitrate for the busses by raising OREQ. When INEN
falls the PCL will start a cycle and set ONPR=1 to indicate that
it is using the busses.
IBSY is latched inside the PCL by two consecutive latches. The
output of the first latch, L1BSY, is used in the generation of
OREQ
and with INEN
to start a cycle.
This latch is open if the PCL is enabled (INEN=0), if the PCL is not attached
(either directly or via multiblock
), and late in a timing
cycle (Strobe 3; OLT=0 &ILT=1).
Thus if the slave is attached, busy and running FASTBUS cycles while another device (eg. an on-board microprocessor (MPU) ) is using the busses BD &OA, L1BSY can only fall during Strobe 3. In particular, it cannot fall just at the beginning of a cycle which could cause contention for OA. Typically there is less problem when IBSY rises since the MPU can only set IBSY when it has control of the busses ( while LBSY=0 and therefore the PCL cannot perform a cycle). (It would be desirable to open the latch all the time a cycle is not in progress, but it is impossible to guarantee the setup time for the latch.)
The output of the second latch, LBSY, is used for all other purposes within the PCL (essentially, generation of SS and abortion of data transfers). This second latch is open early in the timing cycle (Strobe 1; OLT=1 &ILT=0), which allows IBSY to be generated from available address, RD &MS information (eg. implementation of device available logic, where a write to CSR#4 is flagged as busy if the module is allocated). It is also open when the slave is not attached. The user must be careful to meet the setup time of the latch (also ADI latch &parity tree in the case of read cycles); IBSY cannot be driven truly asynchronously from FASTBUS. If asynchronous operation is desired, an external latch must be used to ensure that IBSY is stable at the end of Strobe 1 If such a latch is not used it is possible for a data cycle to be aborted with SS=0, and for unknown data &parity to be returned on a read.
A problem exists using IBSY with a FIFO-like device. If IBSY
rises at the beginning of a read cycle, no data will be returned and SS=1
will be given on FASTBUS, but a short read pulse will be generated which may
cause destructive read to the FIFO. Again, an external latch may be used to
hold IBSY during Strobe 1.