11.7 Application Note #7 - Defeating Parity Logic

Some speed advantage (about 70ns or 25%) may be gained by defeating the parity logic in the PCL/ADI. This may be done by disconnecting the PA and PE segment transceivers, and grounding BPE via a resistor (suggested value 2.2k). ICP may also be grounded. The resistor is required (rather than a direct connection to ground) since BPE is asserted by the PCL during Read cycles.

It is still necessary to connect OCP of the lower ADI to BGPC of the higher ADI as this signal is also used for NTA increment over the 16-bit boundary.