The PCL has three signals that may be used for user side arbitration namely OREQ, ONPR and INEN (Output-Request, Output-Not-PCL-Running and Input-Not-Enable). These signals would be used in an application where the PCL does not have full-time access to the user busses OA and BD, such as in the Slave part of a Host interface.
Under all circumstances the PCL will respond to a primary address cycle. If INEN is high during a Logical address cycle the IA field will not be checked and SS=0 will be returned.
If INEN is low when a FASTBUS data cycle is initiated the cycle will complete in the normal manner. It is not possible to terminate the current cycle by taking INEN high.
If INEN is high and IBSY is high when a FASTBUS data cycle is initiated, the cycle will complete without using OA or BD (OTD remains high), and SS=1 will be returned.
If INEN is high and IBSY is low when a FASTBUS data cycle is initiated, the PCL will assert OWT and OREQ. OWT should drive WT. OREQ is used as a signal to the user bus arbitration logic that the PCL requires the busses. When the current user has released the busses, it drives INEN low for a minimum of 20ns. The PCL then asserts ONPR (indicating that it is using the internal busses) and completes the cycle. OREQ is dropped towards the end of the cycle, but ONPR remains low. When the PCL is ready to accept a new FASTBUS cycle it drops OWT. When it has finished with the internal busses it raises ONPR.
It is necessary to drive ITA on the ADIs in order to release OA when the PCL is not running. ONPR may be used for this purpose directly but this may lead to glitches on OUST during read cycles. Also the time taken for OA to settle will affect the value chosen for the PCL Long Timer.
It is also possible to use OATT as a request to the internal bus arbitration. This will cause the PCL to take control of the internal busses for the entire duration of the FASTBUS operation (which may be extended by segment WT, etc.). Alternatively, a front-end may take control of the internal bus after completion of a triggering Fastbus cycle and lock out Fastbus operations completely with IBSY until it has finished. Which scheme is used will depend on considerations of internal bus latency, acceptable delay on Fastbus, etc.
If the MPU used has only two arbitration signals, such as the Intel 80960's Hold and Hold Acknowledge, it is possible to connect to the PCL using logic such as the following:
!SRQ = (!OREQ & SRQ_ # HOLDA & SRQ_); "SRQ, SRQ_ form an S-R flipflop !SRQ_ = (ONRS & SRQ # !OST & SRQ); "ONRS initializes this !INEN = (HOLDA & SRQ); " enable PCL !HOLD = (OTA & SRQ_); " Hold MPU
Figure 10 shows the relevant waveforms.
Three signals are used for arbitration in the PCL, since it would not be possible to guarantee setup times if the asynchronous PCL was connected to a synchronous MPU using only two lines.