More Generally - Restricting Operation by Modifying User Address Decoder Responses
If it is desired to flag an error in response to an attempt to write a
``Read Only'' location, the IAC must be set to ``Bad
Address'' when RD=0 and OA=the read-only address and OMS=the particular data
operation(s). MS=2 (or 6 or 7) operations must be excluded from this ``Bad
Address'' flag, otherwise a Secondary Address operation with the NTA set to
that location will result in an SS=7 flag. This may be achieved using
OSA
in the address decoder.
Similar action must be taken if it is desired to prevent the use of certain
MS codes at certain addresses. It is strongly recommended that
OMS(2:0) and ORD (from the PCL) be used by the User Address
Decoder for this function, because with a fast Master, due to the pipeline
structure of the PCL, the segment MS and RD signals may not be the same as
those of the current operation. OMS and ORD are the states being used by the
current operation.
There is a situation which needs extra consideration, as follows: OMS and
ORD are up-dated at the start of each cycle (rising edge of Strobe 1). It
takes time for the new states to propagate through the User Address
Decoder to the IAC inputs. The IAC latches are transparent during
Strobe 1 and are locked at the end of Strobe 1 to allow for this propagation
delay. This can result in glitching of signals due to changes in IAC during
Strobe 1.
The User Read Strobe (OUST during a Read of a User Register) is
produced during this time, therefore to prevent possible glitching, OUST is
not suppressed for bad operations. This is not significant if the
location has no readable hardware or is RAM, but if the hardware is a
read-and-clear register or a FIFO
, OUST must be disabled
externally to the PCL to prevent unwanted clearing of the register.
If Logical Addressing is enabled, then the term not AK should be ORed with OSA in the address decoder in order to give a correct SS response to a logical address cycle to dataspace (loading the NTA with the IA field).