11.14 Application Note #14 - Example of CSR#0 Implementation

Figure 17 shows CSR#0 implemented in 74LS series TTL. The parity error bit (labelled CSR14) may optionally be cleared by ONCL rather than ONRS, which would clear it on RB(p) as well as Reset. Table 30 shows the effect of various resets on CSR#0.

The following is an example of implementing part of CSR#0 in a PAL. According to the FASTBUS specification, unused bits should be read back as zero. This may be achieved by putting pull-down resistors on the BD lines, but a more reliable solution is to use tri-state drivers to force BD low at the appropriate time.

module CSR0
title 'Generic CSR#0'

PLA1 device 'P20S10' ;

    ONWZ , ONRS, ONCL, ONPE pin 1,2,3,4 ; " inputs
    ONRZ pin 5 ; " tristate control

    BD16,BD17,BD20,BD21 pin 6,7,8,9 ; " inputs
    BD0,BD1,BD4,BD5,BD14 pin 14,21,16,17,18 ; " bidirects

    IAS, IGK pin 10,11 ; " inputs

    IC01,IC04,IC05,IC14,ISR pin 19,20,15,22,23 ; " outputs

" Macros & definitions
X=.X. ; " don't care
Z=.Z. ; " high impedance
K=.K. ; " negative clock pulse

CLR_PE macro { !(!ONRS # (!IAS & !IGK) ) } ;

JK macro (p,c,j,k,o,q) " J-K flipflop with preset and clear
    { truth_table ([?p,?c,?j,?k,?o,?q] -> ?q)
    "p c j k o q
    [0,1,X,X,X,X] -> 1 ; " async set
    [1,0,X,X,X,X] -> 0 ; " async clear
    [0,0,X,X,X,0] -> 0 ; " async set + clear - nop
    [0,0,X,X,X,1] -> 1 ; " async set + clear - nop
    [1,1,X,X,1,0] -> 0 ; " clock high - nop
    [1,1,X,X,1,1] -> 1 ;
    [1,1,0,0,0,0] -> 0 ; " J=K=0 - nop
    [1,1,0,0,0,1] -> 1 ;
    [1,1,0,1,0,X] -> 0 ; " K clear
    [1,1,1,0,0,X] -> 1 ; " J set
    } ;

JK1 macro (c,j,k,o,q) " J-K flipflop with clear
    { truth_table ([?c,?j,?k,?o,?q] -> ?q)
    "c j k o q
    [0,X,X,X,X] -> 0 ; " async clear
    [1,X,X,1,0] -> 0 ; " clock high - nop
    [1,X,X,1,1] -> 1 ;
    [1,0,0,0,0] -> 0 ; " J=K=0 - nop
    [1,0,0,0,1] -> 1 ;
    [1,0,1,0,X] -> 0 ; " K clear
    [1,1,0,0,X] -> 1 ; " J set
    } ;

    JK1 (ONCL,BD1,BD17,ONWZ,IC01) ; " Enable
    JK1 (ONRS,BD4,BD20,ONWZ,IC04) ; " SR assertion
    JK1 (ONRS,BD5,BD21,ONWZ,IC05) ; " SR flag
    JK (ONPE,CLR_PE,BD14,BD16,ONWZ,IC14) ; " Parity error

equations

    enable IC01 = 1 ; enable IC04 = 1 ;
    enable IC05 = 1 ; enable IC14 = 1 ;

    ISR = IC05 & IC04 ; enable ISR = 1 ;

    BD0 = BD14 ; enable BD0 = !ONRZ ;
    BD1 = IC01 ; enable BD1 = !ONRZ ;
    BD4 = IC04 ; enable BD4 = !ONRZ ;
    BD5 = IC05 ; enable BD5 = !ONRZ ;
    BD14 = IC14 ; enable BD14 = !ONRZ ;

test_vectors
" test ENABLE bit
([ONWZ,ONRZ,ONCL,BD1,BD17] -> [IC01,BD1])
 [1,1,0,0,0] -> [0,Z] ; " reset ONCL 	1
 [1,0,1,Z,Z] -> [0,0] ; " read		2
 [K,1,1,1,0] -> [1,Z] ; " write J	3
 [1,0,1,Z,Z] -> [1,1] ; " read		4
 [K,1,1,0,1] -> [0,Z] ; " write K	5

test_vectors
" test parity error
([ONWZ,ONRZ,ONRS,ONPE,IAS,IGK,BD14,BD16] -> [IC14,BD14])
 [1,1,0,1,1,1,0,0] -> [0,Z] ; " reset ONRS	6
 [1,0,1,1,1,1,Z,Z] -> [0,0] ; " read		7
 [K,1,1,1,1,1,1,0] -> [1,Z] ; " write J		8
 [1,0,1,1,1,1,Z,Z] -> [1,1] ; " read		9
 [K,1,1,1,1,1,0,1] -> [0,Z] ; " write K		10
 [K,1,1,1,1,1,0,0] -> [0,Z] ; " write 0		11
 [K,1,1,1,1,1,1,0] -> [1,Z] ; " write J		12
 [1,1,0,1,1,1,0,0] -> [0,Z] ; " reset ONRS	13
 [1,0,1,1,1,1,Z,Z] -> [0,0] ; " read		14
 [1,1,1,0,1,1,Z,Z] -> [1,Z] ; " parity error ONPE	15
 [1,1,1,1,0,1,Z,Z] -> [1,Z] ; " IAS -> 0	16
 [1,1,1,1,0,0,Z,Z] -> [0,Z] ; " IGK -> 0; RESET	17

test_vectors
" test SR assertion & SR flag
([ONWZ,ONRZ,ONRS,BD4,BD20,BD5,BD21] -> [IC04,IC05,BD4,BD5,ISR])
 [1,1,0,0,0,0,0] -> [0,0,Z,Z,0] ; " reset ONRS18
 [1,0,1,Z,Z,Z,Z] -> [0,0,0,0,0] ; " read	19
 [K,1,1,1,0,1,0] -> [1,1,Z,Z,1] ; " write J	20
 [1,0,1,Z,Z,Z,Z] -> [1,1,1,1,1] ; " read	21
 [K,1,1,0,1,0,0] -> [0,1,Z,Z,0] ; " write K	22

end CSR0