11.12 Application Note #12 - Implementing a Master

There are three methods of using the PCL/ADI set to construct a FASTBUS Master.

One method is to use separate transceivers for the slave and master data paths. A second method would be to tee off the master data path from the BB bus, using the same transceivers as the PCL. In either of these cases the PCL is configured normally as a slave (IMAS is tied low).

The third method, described below, uses the data path in the ADIs for master operations.

When IMAS is high a transmit data path from BD to the AD lines will be set up if RD is low, or from AD to BD if RD is high (i.e. the data flow is reversed from slave operation). The Master part of the Device drives directly RD, MS(2:0), AS, and DS, and receives directly SS(2:0), AK, DK and WT. Note that except for WT, these signal/direction combinations are not used by the Slave part (the PCL). The PCL/ADIs will generate parity and assert BPA, BPE accordingly. The data latch in the ADIs and the parity latch in the PCL are controlled by IMEL, so that a degree of data pipelining may be achieved (not to be confused with the FASTBUS MS=3 Pipelined operation). During a read cycle, parity is checked in the PCL and OMPE is asserted if a parity error occurs. Figure 14 shows two consecutive write cycles and Figure 15 shows two consecutive read cycles. In Figure 15 a parity error occurs on the second read cycle.