BB(15:00) Buffered AD lines: Tri-state, bi-directional. Sixteen address/data lines to be connected via translator-transceivers to the
segment AD lines.
BD(15:00) User Data: Tri-state, bi-directional. Data to and from the user front end.
BGPC Geographic Address Check, Carry in or Parity in: bi-directional. For the
lower chip (INLC = low) this is an output which will be high if the data
on the data bus, bits (04:00) are the same as GA(04:00), and data bus bits
(07:05) are low. For the upper chip, this is the parity input from the lower
chip, but when the NTA register is being incremented it is the carry input
to the adder.
IAW(4:0) Internal Address Width: Inputs. These control the width of the internal
address field recognised by the chip. They must be separately set for
each of the two chips. Input IAW(n) has weight 2. Thus if
all inputs are low, there are no bits in the IA (internal Address) field
of the chip and 16 bits in the DA (Device Address) field. If input IAW2 only
is high, address bits (03:00) are in the IA field and bits (15:04) are in the
DA field. If IAW4 is high then all 16 bits are in the IA field, and the
other IAW inputs have no significance. See the FASTBUS Specification
IGA(4:0) Buffered GA lines: Inputs. For the lower chip these are connected via translators to the geographic
address lines of the FASTBUS segment. The translators should be of the
same type as those used for the AD bus signals. For the upper chip they
may be left open or grounded.
IMXA,IMXB,IMXC Data multiplexer controls: Inputs. These control which of the internal sources drive the internal data bus, as
shown in Table 18 on page .
INLC Not Low Chip: Input. This indicates to a chip if it is the least significant chip or the most
significant chip. It should be permanently wired high or low.
INLC = low for the lower chip, INLC = high for the upper chip
IAMA,IAMB NTA Mux control lines: Inputs. These control which source may be loaded into the NTA register, as
shown in Table 19 on page .
OA(15:00) User Address: Outputs, tri-state. This is the data contained in the NTA register. It is used to address the
OACA,B Address Code A &B: Open collector output. Two decoded address lines; may be connected to further internal address
decoding devices, eg. PLAs. The significance of these signals is as
OCP Carry/Parity Output: Output. This contains the parity check output, or the carry output during increment
NTA operations. For the lower chip output, it should be connected to the
BGPC input of the upper chip. OCP on the upper chip can be used to
detect parity errors or NTA overflow.
OLAC Logical Address Check: Output, open collector. This line is high if,
for bits not masked off as internal address field, the data on the data
bus is identical to the data in CSR#03. OLAC from both chips should be
wire OR-ed, and pulled up with a resistor to +5V.
ONCN Not Class N Check: Output. When low indicates that the class N
register bit selected by internal bus bits (07:04) is set. Only the ONCN
output from the low order ADI chip is used.