7.2 ADI Description

A slave interface requires two ADI chips. The one connected to AD(31:16) is referred to as the upper chip and the one connected to AD(15:00) is referred to as the lower chip. The two chips will perform slightly different functions, for example, only the lower chip is involved in class N detection. The ADI is designed to perform in either position. Each chip knows its position in an interface by the state of the INLC input signal.

A description of the parts of the ADI follows.

• 7.2.1 Data Bus and Multiplexer
• 7.2.2 Data Latch
• 7.2.3 Fastbus Data Buffer
• 7.2.4 User Data Buffer
• 7.2.5 Geographic Address Check
• 7.2.6 Internal Address Width Decode
• 7.2.7 Logical Address Register (CSR#3)
• 7.2.8 Logical Address Check
• 7.2.9 Class N Register (CSR#07)
• 7.2.10 Class N Decoder and Check
• 7.2.11 Next Transfer Address Register
• 7.2.12 User Address Driver
• 7.2.13 Parity Check
• 7.2.14 Address Decoder