7.1 Major Elements of the ADI

• Bi-directional drivers with optional inversion for the Fastbus segment AD translator/drivers;

• Bi-directional drivers with optional inversion for data to and from the user data bus;

• Drivers with optional inversion for a sixteen bit wide address field;

• A sixteen bit wide data buffer latch for pipeline transfer;

• A sixteen bit wide logical address register (CSR#03), with mask control lines to select the required width;

• A sixteen bit wide Class N register (CSR#07),

• Logical address checking, geographical address checking, class N select checking;

• A sixteen bit wide NTA register with loading from the full AD field (secondary address), or selected width (internal address), or the output plus one with full carry cascading (increment);

• Parity generation.