The Protocol Control Logic (PCL)
gate array (LSI Logic L4A0139) has been
designed for use with the Address/Data Interface
(ADI) gate array chips (Fujitsu MB114F307) to provide complete
logic interfacing between a FASTBUS Segment and a FASTBUS Slave device. The
design was developed and simulated on a Daisy Personal Logician CAD
workstation at TRIUMF. The PCL is constructed using an LSI LMA9000 series
CMOS gate array in a plastic package. The ADI is constructed using a Fujitsu
B1100 H series Bipolar gate array in a ceramic package.
The PCL/ADI set is suitable for use in the Slave part of a Master. A control input is provided to allow a Master device proper access to the Segment and to properly attach to its Slave part. The PCL contains arbitration logic on the user side to allow sharing of the user data and address busses with an on-board Micro-Processor. Because of the delay in ECL/TTL translators and to conserve pins on the PCL, FASTBUS Arbitration logic is not included.