7 ADI OPERATION

The Address Data Interface (ADI) has been constructed using a FUJITSU B1100 low power schottky TTL gate array. It uses the equivalent of 1050 three input NAND gates and is mounted in a ceramic RIT88 pin grid package. All signal pins are TTL compatible. The device operates from a 5 volt supply and dissipates approximately 1.6 watts.

• 7.1 Major Elements of the ADI
• 7.2 ADI Description
  • 7.2.1 Data Bus and Multiplexer
  • 7.2.2 Data Latch
  • 7.2.3 Fastbus Data Buffer
  • 7.2.4 User Data Buffer
  • 7.2.5 Geographic Address Check
  • 7.2.6 Internal Address Width Decode
  • 7.2.7 Logical Address Register (CSR#3)
  • 7.2.8 Logical Address Check
  • 7.2.9 Class N Register (CSR#07)
  • 7.2.10 Class N Decoder and Check
  • 7.2.11 Next Transfer Address Register
  • 7.2.12 User Address Driver
  • 7.2.13 Parity Check
  • 7.2.14 Address Decoder
• 7.3 ADI Signal Description
  • 7.3.1 Strobes
  • 7.3.2 Tristate Controls
  • 7.3.3 Inversion Control