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Contents

• Contents
• List of Tables
• List of Figures
• 1 Revisions
• 9.1 Introduction
  • 2.1 Definitions
• 3 Specifications
  • 3.1 Inputs
  • 3.2 Timing
  • 3.3 Power requirements
  • 3.4 Packaging
  • 3.5 FASTBUS addressing modes
  • 3.6 Module ID
• 4 Functional Description
  • 4.1 FASTBUS Slave Interface
    • 4.1.1 ECL-TTL transceivers
    • 4.1.2 Protocol Control Logic
    • 4.1.3 Address Data Interface
    • 4.1.4 Address Decoder
    • 4.1.5 Dataspace Management
    • 4.1.6 CSR#0
    • 9.6.2 Parameter Space
  • 4.2 Encoding
  • 4.3 Error Indicator
  • 4.4 Physical Construction
  • 4.5 Motherboard
  • 4.6 Daughterboard
  • 4.7 Gate Array
• 5 Programmable Features
  • 5.1 Pedestal
  • 5.2 Threshold
  • 5.3 Minimum Pulse Width
  • 5.4 Skirt Width
  • 5.5 Re-read
  • 5.6 Channel disable
  • 5.7 Pedestal disable
  • 5.8 Threshold disable
  • 5.9 Test Mode
  • 5.10 Test Data Generator
• 6 Control Signals
• 7 Restricted Use lines
• 8 Configurable Jumpers
• 9 FASTBUS programming
  • 9.1 Introduction
    • 9.1.1 Advanced Mode
  • 9.2 Register Types
    • 9.2.1 RAM type register
    • 9.2.2 JK type register
    • 9.2.3 FIFO type register
  • 9.3 Primary Addressing
    • 9.3.1 Geographic Addressing
    • 9.3.2 Logical Addressing
    • 9.3.3 Broadcast Addressing
  • 9.4 Secondary addressing
  • 9.5 Data Cycles
  • 9.6 Control and Status Register Space
    • 9.6.1 Normal CSR Space
    • 9.6.2 Parameter Space
    • 9.6.3 User CSR Space
  • 9.7 Data Space
  • 9.8 Parity
• 10 Data Encoding
  • 10.1 Data Analysis
• 11 Initial Checkout
• Index
• About this document ...