CSR#C0000000 through C0000087 provide access to the Data Compactor logic registers.
The sixteen channels have eight registers each. The address in User CSR space for a particular register is given by the following formula:
CSR address = C0000000 + channel 8 + offset
where the offset is given in Table 8.
Thus CSR#C00000000 is the data register for channel 0, etc., through CSR#C000007F which is the last (diagnostic) register for channel 15.
CSR#C0000080 through C000008F are write-only locations. A write operation to one of these registers is effective to all channels, in a similar manner to a general broadcast on the FASTBUS segment. The function of the different registers is given by the formula:
CSR address = C0000080 + offset
The Control/Status registers at offsets 3 and 4 form a JK type register. The bit assignments are given in Tables 9 and 10.
The bit assignments in the Skirt Width register are given in Table 11.
The bit assignments in the MPW register are given in Table 12.
The Minimum Pulse Width is coded as shown in Table 13.
The Skirt Width is coded as shown in Table 14
If a Skirt Width of 3 and an MPW of 3 is selected, the effective MPW is only
2 (ie. a minimum width of 3), due to limitations in the gate array.
The Diagnostic Register (offset 7) is intended to
be used for testing the
gate array and daughter boards during production; programming this register
through FASTBUS may produce anomalous results. The bit assignments are given
in Table 15 for completeness. The default value of the register is
zero; non-zero values cause the output data stream to be replaced with the
output of internal registers. Any non-zero value causes the EOB signal (which
generates SS=2 on FASTBUS) to be replaced by the output of the internal
comparator.
