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Successive read or write cycles access successive data words at the same
Internal address by incrementing an internal pointer.
Following a
block transfer or pipelined cycle, the Next Transfer Address is unchanged.
If the location is unable to accept any more data (for a write), or produce
any more data (for a read), an SS=2 is generated. Note that the optional
protective buffer mechanism described in the FASTBUS specification section
11.3 is not implemented; a single transfer (MS=0) cycle advances the
internal pointer and transfers a new word to or from the FIFO. If a data
transmission error (parity) occurs on a write, the module will issue SS=6
without advancing the internal pointer. The cycle may be immediately re-tried
with no loss of data. If a data transmission error occurs on a read, and
advanced mode is enabled, MS=5 read buffer cycles may be performed until the
data is good, then the original read cycles resumed, with no loss of data. If
advanced mode is not available, the re-read bit may be used which allows for a
re-read of the entire FIFO.
Next: 9.3 Primary Addressing
Up: 9.2 Register Types
Previous: 9.2.2 JK type register