Next: 9.2.3 FIFO type register
Up: 9.2 Register Types
Previous: 9.2.1 RAM type register
During a write operation, bits that are set in the FASTBUS data word become
set in the register. Register bits are cleared by setting a complementary bit
in the FASTBUS data word. For CSR#0, the clear bits are located in the upper
half of the word. For the compactor control registers, the clear bits are
located at the next address.
Following a
block transfer or pipelined cycle, the Next Transfer Address is incremented.
Next: 9.2.3 FIFO type register
Up: 9.2 Register Types
Previous: 9.2.1 RAM type register