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5.9 Test Mode

Test mode may be entered by setting a control bit. In this mode input data to the compactor is taken from FASTBUS rather than from the input buffers. In this way the compactor logic may be exercised using known data without the use of external components, although at a limited speed dictated by the FASTBUS data transfer.



Next: 5.10 Test Data Generator Up: 5 Programmable Features Previous: 5.8 Threshold disable


A.Daviel,TRIUMF