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On some versions of the module, a Test Data Generator is implemented. This
may be loaded with known data via FASTBUS and used to exercise the compactor
logic and input data buffers at full speed. The Test Data is loaded using
CSR#1, and the generator is controlled by User bits in CSR#0.
If the components for test data generator are not fitted, jumpers
JP3 and JP4 must be fitted to prevent spurious signals being
generated on the clock and envelope lines (TR0, TR1).
Next: 6 Control Signals
Up: 5 Programmable Features
Previous: 5.9 Test Mode