Figure 3 shows the main features of the gate array.
Operation of the compactor array is controlled by an external clock synchronized with the CCD data. The pedestal is first subtracted from the 8-bit input data . The resulting data is then compared with a preset threshold value. Data which is above threshold is passed to the output where it is assembled into 32-bit words in the external data FIFOs. The passing of data to the output is also controlled by the Skirt Width logic. The Header Generator inserts bin and address counts into the output data stream to preserve the timing information
The diagnostic register provides access to internal data paths. This is used for testing the array during manufacture.