module will assert PE, and PA as appropriate, on any read operation. For a
write operation, if PE is asserted by the Master (or Segment Interconnect),
the module will check PA. If the parity is correct, the operation will
proceed normally. If it is incorrect, the response depends on the particular
operation. For a Primary Address, the module will not connect (AK=0).
For a Secondary Address, the module will issue SS=7, and issue SS=6 to any
subsequent data operations (since the Internal Address is invalid). For a
Data Write, the module will issue either SS=6 (rejecting the data),
or SS=7 (accepting the data), depending on the state of the IACT
jumper. If a parity error occurs while the module is attached, the parity
flag (CSR#0
) and error flag (CSR#0
) will be set. The
parity flag may be cleared explicitly by writing the clear error bit
(CSR#0
), or implicitly by dropping AS and GK (releasing mastership
of the segment).
Some speed advantage may be gained by disabling parity. To take advantage of
this, it is necessary to reduce the length of the Long Timer. This may be
accomplished by replacing R26 (nominal 750) with 330
.