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The module will respond at all valid internal address values to data cycles
with MS=0 (single transfer, FRC or FRD), MS=1 (block transfer, FRCB or FRDB),
and MS=3 (pipeline transfer). If advanced mode is enabled the module will
also respond to data cycles with MS=4 (single transfer). SS responses are
generated as shown in Table 5.
The generation of SS codes may be modified by jumpers on the board; see
Section 8.
Next: 9.6 Control and Status
Up: 9 FASTBUS programming
Previous: 9.4 Secondary addressing