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The Internal Address register is 32 bits wide. It is set to zero by a logical
address cycle to dataspace, and may be written by a data cycle with
MS=2 or, if advanced mode is enabled, by a data cycle with MS=6 or MS=7.
It may be read back by a corresponding read data cycle. A secondary address
cycle (read or write) with an invalid secondary address will generate an SS=7
response. If parity is enabled a write secondary address cycle with bad
parity will also generate an SS=7 response.
Next: 9.5 Data Cycles
Up: 9 FASTBUS programming
Previous: 9.3.3 Broadcast Addressing