Operation of the data compactor gate arrays is controlled by two signals, Clock and Envelope, which must be provided to the module on the FASTBUS backplane (see section 7 ).
The Clock signal is held at zero in the quiescent state, and pulses high during readout of the CCD. Clock pulses are required to continue for a period immediately following CCD readout (normally for a period equal to the readout time); a minimum of 10 clock pulses are required to clear the compactor pipelines and build the channel header. Thus for a 128-bin CCD there would normally be 256 consecutive clock pulses. The compactor uses the rising edge of the Clock signal to strobe in the input data from the CCD module. The compactor also uses the clock signal to read the pedestal FIFO. This feature requires that the mark (or high) state of the clock be a minimum of 10ns, and that the space (or low) state of the clock be a minimum of 20ns in order to meet the timing requirements of the FIFO.
The Envelope signal is true during the readout time of the CCD, otherwise false. For a 128-bin CCD it would be high for 128 clock cycles and low thereafter. The compactor uses the rising edge of the Envelope signal to generate an internal reset pulse. This reset pulse clears the output buffers, internal counters and internal latches.
Data from the CCD is digitized towards the end of a clock cycle; the clock for the compactor is generated in the middle of a clock cycle. This means that there is no data associated with the first clock pulse seen by the compactor. The compactor uses this pulse to reset the pedestal FIFO. Conversely, the last data byte is associated with the first clock pulse after the falling edge of the Envelope signal.
Figure 6 shows the timing of the control signals for a normal operation.
If the operation is aborted during compaction, the Envelope signal and the Clock are both taken low immediately.
Figure 7 shows the timing of the control signals for an aborted operation.