4 Functional Description

The device consists of three different components; a FASTBUS Slave interface, sixteen daughter boards containing the Data Compaction logic, and an input signal receiver section.

• 4.1 FASTBUS Slave Interface
  • 4.1.1 ECL-TTL transceivers
  • 4.1.2 Protocol Control Logic
  • 4.1.3 Address Data Interface
  • 4.1.4 Address Decoder
  • 4.1.5 Dataspace Management
  • 4.1.6 CSR#0
  • 9.6.2 Parameter Space
• 4.2 Encoding
• 4.3 Error Indicator
• 4.4 Physical Construction
• 4.5 Motherboard
• 4.6 Daughterboard
• 4.7 Gate Array