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Figure 2 shows one daughterboard.
Most of the functionality of the daughterboard is contained in the gate array. External FIFO memories are used to reduce the gate and pin count of the array, so that a smaller array may be used.
The 8-bit control bus to the gate array is multiplexed with the 32-bit output data bus from the data FIFOs. Pedestal data is loaded into the pedestal FIFO, and clocked into the gate array synchronously with the input data.
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