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vi Performance

One module with sixteen channels has been successfully used in Experiment 787[5] at Brookhaven National Laboratory. For this run the CCD output clock rate was set at 16MHz, half the design frequency, as a result of changes to the CCD module.

For the production quantity of 1024 channels, the gate array design has been modified to correct some problems found during prototype testing. The maximum skirt width has also been increased from 2 to 3.

Next: vii Conclusions Up: A 30MHz FASTBUS Previous: v Testing