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v Testing

The gate arrays are tested after manufacture using some 7000 test vectors generated during design simulation. Each daughterboard is tested during production using a custom PC-based test station. Complete modules are tested using FASTBUS software.

The gate array incorporates a `test mode' where synthetic input data may be written to each channel via FASTBUS. Using this feature, the complete data path (with the exception of the ECL receivers) may be tested via FASTBUS.

Selected modules have been fitted with a Test Data Generator which enables the injection of synthetic data at the front panel inputs at the full data rate. This method is used for initial testing, and may be used after installation if the input cables are removed.

The same data sets were used in simulation, in the daughterboard test station, and for complete module tests.



Next: vi Performance Up: A 30MHz FASTBUS Previous: iv Simulation



A.Daviel,TRIUMF